1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit capable of executing an I/O test of data.
2. Related Art
In conventional systems, interface circuits are provided between a semiconductor integrated circuit and a controller for controlling the semiconductor integrated circuit. Often, however, there is a skew between the interfaces between the semiconductor integrated circuit and the controller. If the skew exceeds a predetermined range, then data transmission error can occur.
Accordingly, a data transmission test has to be performed in order to confirm whether data transmission is carried out normally by a particular semiconductor integrated circuit. The data transmission test is carried out in such a manner that a specific data pattern is communicated between the semiconductor integrated circuit and the controller.
For the execution of the data transmission test, a conventional semiconductor integrated circuit uses memory cells which are provided for normal data storage in the vicinity of the I/O circuit or uses additional memory cells, which are different from those configured for normal data storage. Using additional memory cells provided in the I/O circuit requires additional area and creates complicated timing control and metal wires. Furthermore, using memory cells configured for normal data storage can cause excessive current consumption in activating word lines and sensing data of bit lines. This excessive current consumption can cause noise and errors in the data transmission test.